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vishay TFDU6108 document number 82537 rev. 1.6, 25-jun-04 vishay semiconductors www.vishay.com 1 18102 fast infrared transceiver module (4 mbit/s), irda ? serial interface compatible, 2.7 v to 5.5 v supply voltage range description the TFDU6108 is an infrared transceiver module compliant to the latest irda standard for fast infrared data communication, supporting irda speeds up to 4.0 mbit/s (fir), and carrier based remote control modes up to 2 mhz. integrated within the transceiver module are a pin photodiode, an infrared emitter (ired), and a low-power cmos control ic to provide a total front-end solution in a single package. these fir transceivers with an integrated serial inter- face are compliant with the irda "serial interface standard for transceiver control". the transceivers are capable of directly interfacing with a wide variety of i/o devices, which perform the modulation/ demodulation function. at a minimum, a v cc bypass capacitor is the only external component required implementing a complete solution. for limiting the transceiver internal power dissipation one additional resistor might be added. the transceiver can be oper- ated with logic i/o voltages as low as 1.5 v. new features ? the functionality of the device is similar to the tfdu6102 series. the irda compatible serial interface function is replacing the former program- ming method, guaranteeing a perfect irda stan- dardized and compliant programmability. the ired current is programmable to different levels, no external current limiting resistor is necessary. features compliant to the latest irda physical layer specifi- cation (up to 4 mbit/s) tv remote control compliant to the irda "serial interface specifica- tion for transceivers" for 3.0 v and 5.0 v applications, fully specified 2.7 v to 5.5 v operational down to 2.6 v compliant to all logic levels between 1.5 v and 5 v low power consumption (typ. 2.0 ma supply current) power shutdown mode (< 1 a shutdown current) surface mount package options - universal (l 9.7 mm w 4.7 mm h 4.0 mm) - side and top view tri-state-receiver output, weak pull-up when in shutdown mode high efficiency emitter baby face (universal) package capable of surface mount soldering to side and top view orientation eye safety class 1 (iec60825-1, ed. 2001), limited led on-time, led current is controlled, no single fault to be considered built - in emi protection including gsm bands. emi immunity in gsm bands > 300 v/m verified no external shielding necessary few external components required pin to pin compatible to legacy vishay semicon- ductor sir and fir infrared transceivers split power supply, transmitter and receiver can be operated from two power supplies with relaxed requirements saving costs, us patent no. 6,157,476 compliant with irda emi and background light specification applications notebook computers, desktop pcs, palmtop computers (win ce, palm pc), pdas printers, fax machines, photocopiers, screen projectors telecommunication products (cellular phones, pagers) internet tv boxes, video conferencing systems external infrared adapters (dongles) medical and industrial data collection devices
www.vishay.com 2 document number 82537 rev. 1.6, 25-jun-04 vishay TFDU6108 vishay semiconductors parts table functional bloc k diagram pin description part description qty / reel TFDU6108-tr3 oriented in carrier tape for side view surface mounting 1000 pcs TFDU6108-tt3 oriented in carrier tape for top view surface mounting 1000 pcs comparator amplifier agc logic driver current controlled driver v cc1 sclk txd gnd rxd ired anode ired cathode 200 v logic v cc2 17086 ? ? ). pin is current limited for protection against bus collisions due to programming errors. olow 5 sclk serial clock, dynamically loaded for noise suppression. i high 6v cc supply voltage 7v logic supply voltage for digital part, 1.5 v to 5.5 v, defines logic swing for txd, sclk, and rxd 8 gnd ground
vishay TFDU6108 document number 82537 rev. 1.6, 25-jun-04 vishay semiconductors www.vishay.com 3 pinout TFDU6108 weight 200 mg definitions: in the vishay transceiver data sheets the following nomenclature is used for defining the irda operating modes: sir: 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared standard with the physical layer version irphy 1.0 mir 576 kbit/s to 1152 kbit/s fir 4 mbit/s vfir 16 mbit/s mir and fir were implemented with irphy 1.1, followed by irphy 1.2, adding the sir low power standard. irphy 1.3 extended the low power option to mir and fir and vfir was added with irphy 1.4. a new version of the standard in any obsoletes the former ver- sion. absolute maximum ratings reference point ground (pin 8) unless otherwise noted. typical values are for design aid only, not guaranteed nor subject to production testing. *) due to the internal measures the dev ice is a "class1" device. it will not exceed the irda intensity limit of 500 mw/sr. "u" option babyface (universal) ired detector 12345678 17087 parameter test conditions symbol min ty p. max unit supply voltage range, transceiver 0 v < v cc2 < 6 v v cc1 - 0.5 + 6 v supply voltage range, transmitter 0 v < v cc1 < 6 v v cc2 - 0.5 + 6 v supply voltage range, transceiver logic 0 v < v cc1 < 6 v v logic - 0.5 + 6 v input currents for all pins, except ired anode pin 10 ma output sinking current 25 ma junction temperature t j 125 c power dissipation see derating curve, figure 4 p d 350 mw ambient temperature range (operating) t amb - 25 + 85 c storage temperature range t stg - 40 + 100 c soldering temperature see recommended solder profile (see figure 3) 240 c average output current i ired (dc) 130 ma repetitive pulse output current < 90 s, t on < 20 % i ired (rp) 600 ma ired anode voltage v ireda - 0.5 + 6 v transmitter data input voltage v txd - 0.5 v logic + 0.5 v receiver data output voltage v rxd - 0.5 v logic + 0.5 v virtual source size method: (1 - 1/e) encircled energy d2.52.8 mm maximum intensity for class 1 operation of iec825-1 or en60825-1, edition jan. 2001*) irda specified maximum limit unidirectional operation, worst case irda fir pulse pattern internally limited to class 1 500 mw/sr
www.vishay.com 4 document number 82537 rev. 1.6, 25-jun-04 vishay TFDU6108 vishay semiconductors electrical characteristics transceiver t amb = 25 c, v cc = 2.7 v to 5.5 v unless otherwise noted. typical values are for design aid only, not guaranteed nor subject to production testing. 1) receive mode only. in transmit mode, add the av eraged programmed current of ired current as i cc2 2) standard illuminant a 3) the typical threshold level is between 0.5 x v logic /2 (v logic = 3 v) and 0.4 x v logic (v logic = 5.5 v). with that the device will work with less tight levels than the specified min/ max values. however, it is recommended to use the specified min/max values to avoid increa sed oper- ating/standby supply currents. parameter test conditions symbol min ty p. max unit supply voltage v cc1 2.7 5.5 v v logic 1.5 5.5 v dynamic supply current 1) t = - 25 c to 85 c active, no signal e e = 0 klx i cc1 2.0 2.35 ma t = 25 c 2.3 ma t = - 25 c to 85 c idle active, no load e e = 0 klx i logic 5 a t = - 25 c to 85 c e e = 1 klx 2) receive mode, e eo = 100 mw/m 2 (9.6 kbit/s to 4.0 mbit/s), rl = 10 k ? to v logic = 5 v, cl = 15 pf i logic 160 1 a shutdown supply current inactive, set to shutdown mode t = 25 c, e e = 0 klx i sd 1 a inactive, set to shutdown mode t = 25 c, e e = 1 klx 2) i sd 1.5 a shutdown mode, t = 85 c, not ambient light sensitive i sd 5 a operating temperature range t a - 25 + 85 c output voltage low c load = 15 pf, v logic = 5 v v ol 0.5 0.8 v output voltage high c load = 15 pf, v logic = 5 v v oh v logic - 0.5 v input voltage low (txd, sclk) cmos level 3) v il 0.15 2) v logic v input voltage high (txd, sclk) cmos level 3) v ih 0.9 2) v logic v input leakage current (txd, sclk) i l - 10 + 10 a input capacitance c in 5pf
vishay TFDU6108 document number 82537 rev. 1.6, 25-jun-04 vishay semiconductors www.vishay.com 5 input load the waveform "i ddadd " shows the additional operat- ing current of one input buffer (in this case txd) vs. the logic input voltage v (txi) for the digital supply voltage v dd = 3 v under typical working conditions. the current "i vic " is the typical input current vs. the input voltage. optoelectronic characteristics receiver t amb = 25 c, v cc = 2.7 v to 5.5 v unless otherwise noted. typical values are for design aid only, not guaranteed nor subject to production testing. -0.5 0.0 0.5 1.0 1.5 2.0 2.5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 ms 3.0 3.5 10 -4 i ddad a 17088 -1.5 -1.0 -0.5 0.0 0.5 1.0 10 -5 i vic a - 0.01 0.00 0.01 0.02 0.03 0.04 0.05 0.06 a i vdiode -1 0 1 2 3 4 5 6 7 v v (tx1) parameter test conditions symbol min ty p. max unit minimum detection threshold irradiance, sir mode 9.6 kbit/s to 115.2 kbit/s = 850 nm to 900 nm e e 25 40 mw/m 2 minimum detection threshold irradiance, mir mode 1.152 mbit/s = 850 nm to 900 nm e e 65 mw/m 2 minimum detection threshold irradiance, fir mode 4.0 mbit/s = 850 nm to 900 nm e e 85 90 mw/m 2 maximum detection threshold irradiance = 850 nm to 900 nm e e 510 kw/m 2
www.vishay.com 6 document number 82537 rev. 1.6, 25-jun-04 vishay TFDU6108 vishay semiconductors transmitter t amb = 25 c, v cc = 2.7 v to 5.5 v unless otherwise noted. typical values are for design aid only, not guaranteed nor subject to production testing. logic low receiver input irradiance optical ambient noise suppression up to this level for e.g. fluorescent light tolerance equivalent to the irda ? "background light and electromagnetic field" specification e e 4 mw/m 2 rise time of output signal 10 % to 90 %, @ 2.2 k ? , 15 pf t r (rxd) 40 ns fall time of output signal 90 % to 10 %, @ 2.2 k ? , 15 pf t f (rxd) 40 ns rxd pulse width of output signal, 50 % sir mode input pulse length 20 s, 9.6 kbit/s t pw 1.3 2 3 s input pulse length 1.41 s, 115.2 mbit/s t pw 1.2 3 s rxd pulse width of output signal, 50 % mir mode input pulse length 217 ns, 1.152 mbit/s t pw 110 260 ns jitter, leading edge, mir mode input irradiance = 100 mw/m 2 , 1.152 mbit/s 20 ns rxd pulse width of output signal, 50 % fir mode input pulse length 125 ns, 4.0 mbit/s t pw 100 160 ns jitter, leading edge, fir mode input irradiance = 100 mw/m 2 , 4 mbit/s 20 ns latency t l 120 s parameter test conditions symbol min ty p. max unit ired operating current internally controlled, programmable using the "serial interface" programming sequence, see appendix v cc1 = 3.3 v, the maximum current is limited internally. an external resistor can be used to reduce the power dissipation at higher operating voltages, see derating curve. i d 8 15 30 60 110 220 500 600 ma max. output radiant intensity v cc1 = 3.3 v, = 0 , 15 , txd = high, r1 = 0 ? programmed to max. power level i e 0.3 mw/sr/ma output radiant intensity v cc1 = 3.3 v, = 0 , 15 , txd = low, r1 = 0 ? programmed to shutdown mode i e 0.04 mw/sr output radiant intensity, angle of half intensity 24 peak - emission wavelength p 880 900 nm spectral bandwidth ? 40 nm optical rise time, fall time t ropt , t fopt 10 40 ns optical overshoot 10 % parameter test conditions symbol min ty p. max unit
vishay TFDU6108 document number 82537 rev. 1.6, 25-jun-04 vishay semiconductors www.vishay.com 7 recommended circuit diagram operated with a low impedance power supply the TFDU6108 needs no external components. however, depending on the entire system design and board lay- out, additional components may be required (see fig- ure 1). vishay semiconductor transceivers integrate a sensi- tive receiver and a built-in power driver. the combina- tion of both needs a careful circuit board layout. the use of thin, long, resistive and inductive wiring should be avoided. the inputs (txd, sclk) and the output rxd should be directly (dc) coupled to the i/o circuit. r1 is used for controlling the maximum current through the ir emitter. this one is necessary when operating over the full range of operating temperature and v cc1 - voltages above 4 v. for increasing the max. output power of the ired, the value of the resis- tor should be reduced. it should be dimensioned to keep the ired anode voltage below 4 v for using the full temperature range. for device and eye protection the pulse duration and current are internally limited. r2, c1 and c2 are optional and dependent on the quality of the supply voltage v cc1 and injected noise. an unstable power supply with dropping voltage dur- ing transmission may reduce sensitivity (and trans- mission range) of the transceiver. the placement of these parts is critical. it is strongly recommended to position c2 close to the transceiver power supply pins. an electrolytic capacitor should be used for c1 while a ceramic capacitor is used for c2. recommended application circuit components i/o and software for operating the device from a controller i/o a driver software must be implemented. mode switching the generic irda "serial interface programming" needs no special settings for the device. only the cur- rent control table must be taken into account. for the description see the appendix and the irda "serial interface specification for transceivers" figure 1. recommended application circuit all external components (r, c) are optional ired cathode ired anode rxd vcc gnd txd sclk v logic c2 c1 r2 r1 v cc2 rxd gnd v cc1 sclk txd v logic 17089 component recommended value c1 4.7 f, 16 v c2 0.1 f, ceramic, 16v r1 recommended for v cc1 4 v depending on current limit r2 47 ? , 0.125 w
www.vishay.com 8 document number 82537 rev. 1.6, 25-jun-04 vishay TFDU6108 vishay semiconductors recommended solder profile solder profile for sn/pb soldering lead-free, recommended solder profile the TFDU6108 is a lead-free transceiver and quali- fied for lead-free processing. for lead-free solder paste like sn (3.0 - 4.0) ag (0.5 - 0.9) cu, there are two standard reflow profiles: ramp-soak-spike (rss) and ramp-to-spike (rts). the ramp-soak-spike profile was developed primarily for reflow ovens heated by infrared radiation. shown below in figure 3 is vishay?s recommended profile for use with the TFDU6108 transceivers. for more details please refer to application note: smd assembly instruction. figure 2. recommended solder profile time(s) 14874 0 20 40 60 80 100 120 140 160 180 200 220 240 0 50 100 150 200 250 300 350 2 c-4 c/s 10 s max. @ 230 c 90 s max 120 s - 180 s 2 c-4 c/s temperature (c) t = 250c for 20 s max 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 0 50 100 150 200 250 300 350 time/s 20 s max. 2c...4c/s 2c...4c/s t = 217c for 50 s max t peak = 260c max. 50 s max. 90 s...120 s 19048 temperature/ c figure 3. solder profile, rss recommendation
vishay TFDU6108 document number 82537 rev. 1.6, 25-jun-04 vishay semiconductors www.vishay.com 9 current derating diagram figure 4. current derating diagram 0 100 200 300 400 500 600 ?40 ?20 0 20 40 60 80 100 120 140 peak operating current ( ma ) temperature ( c ) 14875 current derating as a function of the maximum forward current of ired. maximum duty cycle: 25%.
www.vishay.com 10 document number 82537 rev. 1.6, 25-jun-04 vishay TFDU6108 vishay semiconductors package dimensions in mm 18473
vishay TFDU6108 document number 82537 rev. 1.6, 25-jun-04 vishay semiconductors www.vishay.com 11 appendix a serial interface implementation basics of the irda definitions the data lines are multiplexed with the transmitter and receiver signals and separate clocks are used since the transceivers respond to the same address. when no infrared communication is in progress and the serial bus is idle, the irtx line is kept low and irrx is kept high. 17092 figure 5. interface to two infrared transceivers 17093 figure 6. infrared dongle with differential signaling
www.vishay.com 12 document number 82537 rev. 1.6, 25-jun-04 vishay TFDU6108 vishay semiconductors functional description the serial interface is designed to interconnect two or more devices. one of the devices is always in control of the serial interface and is responsible for starting every transaction. this device functions as the bus master and is always the infrared controller. the infra- red transceivers act as bus slaves and only respond to transactions initiated by the master. a bus transac- tion is made up of one or two phases. the first phase is the command phase and is present in every trans- action. the second phase is the response phase and is present only in those transactions in which data must be returned from the slave. if the operation involves a data transfer from the slave, there will be a response phase following the command phase in which the slave will output the data. the response phase, if present, must begin 4 clock cycles after the last bit of the command phase, as shown in figures 1 - 7 and 1 - 8, otherwise it is assumed that there will be no response phase and the master can terminate the transaction. the sclk line is always driven by the master and is used to clock the data being written to or read from the slave. this line is driven by a totem-pole output buffer. the sclk line is always stopped when the serial interface is idle to minimize power consumption and to avoid any interference with the analog circuitry inside the slave. there are no gaps between the bytes in either the command or response phase. data is always transferred in little endian order (least significant bit first). input data is sampled on the rising edge of sclk. irtx/swdat output data from the controller is clocked by sclk falling edge. irrx/srdat output data from the slave is clocked by sclk rising edge. each byte of data in both command and response phases is preceded by one start bit. the data to be written to the slave is carried on the irtx/swdat line. when the control interface is idle, this line carries the infrared data signal used to drive the transmitter led. when the first low-to-high transition on sclk is detected at the beginning of the command sequence, the slave will disable the transmitter led. the infrared controller then outputs the command string on the irtx/swdat line. on the last sclk cycle of the command sequence the slave re-enables the trans- mitter led and normal infrared transmission can resume. no transition on sclk must occur until the next command sequence otherwise the slave will dis- able the transmitter led again. read data is carried on the irrx/srdat line. the slave disables the internal signal from the receiver photo diode during the response phase of a read transaction. the addressed slave will output the read data on the irrx/srdat line regardless of the setting of the receiver output enable bit in the mode selection reg- ister 0. non addressed slaves will tri-state the irrx/ srdat line. when the transceiver is powered up, the irtx/swdat line should be kept low and sclk should be cycled at least 30 times by the infrared con- troller before the first command is issued on the irtx/ swdat line. this guarantees that the transceiver interface circuitry will properly initialize and be ready to receive commands from the controller. in case of a multiple transceiver configuration, only one trans- ceiver should have the receiver output enabled. a series resistor (approx. 200 ohms) should be placed on the receiver output from each transceiver to pre- vent large currents in case a conflict occurs due to a programming error. figure 7. initial reset timing figure 8. special command waveform sclk irtx/ swdat irrx/ srdat tled_dis (internal signal) 17175 sclk irtx/ swdat irrx/ srdat tled_dis (internal signal) res (internal signal) (note 1) 17176
vishay TFDU6108 document number 82537 rev. 1.6, 25-jun-04 vishay semiconductors www.vishay.com 13 note 1: if the apen bit in control register 0 is set to 1, the internal signal from the receiver photo diode is discon nected and the irrx/ srdat line is pulsed low for one clock cycle at the end of a write or special command. note 2: during a read transaction the infrared controller sets the irtx/swdat line high after sending the address and index byte (or bytes). it will then set it low two clock cycles before the end of the transaction. it is strongly recommended that optical transceiv- ers monitor this line instead of counting clock cycles in order to detect the end of the read trans action. this will always guarantee correct operation in case two or more transceivers from different manufacturers are sharing the serial interface. figure 9. write data waveform figure 10. write data waveform with extended index 17177 17178 figure 11. read data waveform figure 12. read data waveform with extended index 17179 17180
www.vishay.com 14 document number 82537 rev. 1.6, 25-jun-04 vishay TFDU6108 vishay semiconductors switching characteristics maximum capacitive load = 20 pf 1) 1) capacitive load is different from "serial interf ace - specification". for the bus protocol see "recommended serial interface for transceiver control, draft ve rsion 1.0a, march 29, 2000, irda" . in appendix b the transceiver related data are given. parameters test conditions symbol min. max. unit sclk clock period r.e., sclk to next r.e., sclk tckp 250 infinity ns sclk clock high time at 2.0 v for single-ended signals tckh 60 ns sclk clock low time at 0.8 v for single-ended signals tckl 80 ns output data valid (from infrared controller) after f.e., sclk tdotv 40 ns output data hold (from infrared controller) after f.e., sclk tdoth 0 ns output data valid (from optical transceiver) after r.e., sclk tdorv 40 ns output data hold (from optical transceiver) after r.e., sclk tdorh 40 ns line float delay after r.e., sclk tdorf 60 ns input data setup before r.e., sclk tdis 10 ns input data hold after r.e., sclk tdih 5 ns
vishay TFDU6108 document number 82537 rev. 1.6, 25-jun-04 vishay semiconductors www.vishay.com 15 appendix b application guideline in the following some guideline is given for handling the TFDU6108 in an application ambient, especially for testing. it is also a guideline for interfacing with a controller. we recommend to use for first evaluation the vishay irm1802 controller. for more information see the special data sheet. driver software is avail- able on request. contact irdc@vishay.com. serial interface capa bility of the vishay irda transceivers abstract a serial interface allows an infrared controller to com- municate with one or more infrared transceivers. the basic specification of irda ? specified interface is described in "serial interface for transceiver control, v 1.0a", irda. this part of the document describes the capabilities of the serial interface implemented in the vishay irda transceivers tfdu8108 and TFDU6108. the vfir (16 mbit/s) and fir (4 mbit/s) programmable versions are using the same interface specification (with spe- cific identification and programming). irda serial interface basics the s erial i nterface for t ransceiver c ontrol (sitc) is a master/slave synchronous serial bus which uses the txd and rxd as data lines and the sclk as clock line with a minimum period of 250 ns. the transceiver works always as slave and jump into sitc mode on the first rising edge of the clock line remaining there until the command phase is finished. after power on it is required an initial phase for 30 clock cycles at txd is continuous low before the transmitter can be pro- grammed. if txd assume high during the initial phase then must start the initial phase again. the data transfer is organized by one byte preceded by one start bit. the sitc allows the communication between infrared controller and transceiver through write and read transaction. the sitc consists of two store blocks with different functions. the store block called extended indexed registers contain the vari- ous supported functionality of the device and can be read only. the other main control registers allow write and read transaction and store the executable configuration of the device. any configuration is executed after the command phase is completed. power - up defaults after power on the transceiver has to stay by definition in the following default mode shown in the table. the default mode of the TFDU6108 is different from the originally defined irda serial interf ace default mode. the implemented deviation from the standard was a market re- quest because only in this way a requested quick function test is possible with the TFDU6108 without the need to connect to a p rogramming device. addressing the transceiver is addressable with three address bits. there are individual and common addresses with the following values. function TFDU6108 power mode active (!) rx active tx_led active apen enabled infrared mode sir transmitter power defined sir level description address value a [2:0] individual address mask programmable 001 common (broadcast) address 111
www.vishay.com 16 document number 82537 rev. 1.6, 25-jun-04 vishay TFDU6108 vishay semiconductors data acknowledgement data acknowledgement generated by the slave is available if the apen bit is set to 1 in the common control register. in irda default state this functionality is disabled. in default state of the TFDU6108 it is enabled (see above). it is strongly recommended that this functionality is enabled to be on the safe side for correct data transmission during sitc mode. registers data depth in general the whole data registers consist of a data depth of eight bits. but sometimes it is unnecessary to implement the full depth. in such a case the invisible bits consider like a zero. used index commands the table shows the valid index commands, its allowable modes, and the data depth to them. main-ctrl-0 register values 1) apen - acknowledge pulse enable, (optional) this bit is used to enable the acknowledge pulse. when it is se t to 1 and rx oen is 1 (receiver output enabled) the irrx/srdat line will be pulsed low for one clock cycle upon successful completion of every write command or special command with individual (non bro adcast) transceiver address. the internal signal from the receiver photo diode is disconnected when this bit is set to 1. commands index [3:0] mode action register name data bits default value TFDU6108 0h w/r common control main-ctrl-0 register [4.2:0] 14h 1h w/r infrared mode main-ctrl-1 register [3:0] 00h 2h w/r txd power level main-ctrl-2 register [7:4] 70h bh - 3h x not used ch x not used dh w reset transceiver, only one byte! r not used eh x not used fh w not used r extended indexing value function default bit 0 pm sl - power mode select 0 low power mode (sleep mode) 1 normal operation power mode active (!) bit 1 rx oen - receiver output enable 0 irrx/srdat line disable (tri-stated) 1 irrx/srdat line enabled active bit 2 tled en - transmitter led enable 0 disabled 1 enabled active bit 3 not used not used bit 4 apen 1) enabled
vishay TFDU6108 document number 82537 rev. 1.6, 25-jun-04 vishay semiconductors www.vishay.com 17 main-ctrl-1 register values if any other value is tried to be written by the controller in to the sif, the transceiver will load 00h into the main_crtl_1 re gister and will not give an acknowledgement main-ctrl-2 register values 1) default setting used extended i ndexed registers the table shows the valid extended indexed commands its allowable modes and the data depth to them. value function bit 0 sir (default) bit 1 mir bit 2 fir bit 3 sharp ir ? apple talk ? (sir functionality) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mode txd-ired (ma) remark 8xh- fxh 1xxxxxxx fir > 1 m, not for sir! 550 (switch, ext. r1!) fir standard, serial resistor is necessary for v cc2 > 4 v 7xh 1) 0111xxxx sir >1 m fir > 0.7 m 250 sir more ext. fir lp 6xh 0 1 1 0 sir > 0.70 m fir > 0.45 m 125 extended fir low power 5xh 0 1 0 1 sir > 0.50 m fir > 0.30 m 60 fir low power 4xh 0 1 0 0 (45) 3xh 0 0 1 1 sir > 0.35 m fir > 0.20 m 30 sir low power 2xh 0 0 1 0 sir > 0.25 m fir > 0.15 m 15 e.g. docking station 1xh 0 0 0 1 sir > 0.15 m fir > 0.10 m 8 e.g. docking station 0xh0000xxxx 0 register address e_index [7:0] mode action data bits fixed value 00h r manufactured id [7:0] 0:4h 01h r device id [7:0] [7:6] 11 04h r receiver recovery time power on stabilization [6:4, 2:0] 24h 05h r receiver stabilization sckl max. frequency [6:4, 2:0] 30h 06h r common capabilities [7:0] 03h 07h r supported infrared modes [7:0] 0fh 08h r supported infrared modes 0 01h
www.vishay.com 18 document number 82537 rev. 1.6, 25-jun-04 vishay TFDU6108 vishay semiconductors
vishay TFDU6108 document number 82537 rev. 1.6, 25-jun-04 vishay semiconductors www.vishay.com 19 invalid commands handling there are some commands and register addres ses, which cannot be decoded by the sitc. the slave ignores such invalid data for th e internal logic. below the different types and the slave reaction to them are shown. no reaction means that the slav e does not start the respond phase. reset there is no external reset pin at vishay irda trans- ceivers. in case of transition error there are two ways to set the sitc in a defined state: the first one is power off. the second one is that the transceiver monitors the irtx/swdat line in any state. if this line is assumed low for 30 clock cycles then the trans- ceiver must be set to the command start state and set all registers to default implemented values. description master command slave reaction on irrx/srdat invalid command in read mode index [3:0] & c = 0 no reaction invalid command in write mode index [3:0] & c = 1 no acknowledgement generating independent of the value of apen valid command in invalid read mode index [3:0] & c = 0 no reaction valid command in invalid write mode index [3:0] & c = 1 no acknowledgement generating independent of the value of apen valid command in invalid write mode and invalid data index [3:0] & c = 1 no acknowledgement generating independent of the value of apen broadcast (common) address in read mode a [2:0] = 111 & c = 0 no reaction
www.vishay.com 20 document number 82537 rev. 1.6, 25-jun-04 vishay TFDU6108 vishay semiconductors appendix c serial interface (sif) programming guide the sif port of this module allow an ir controller to communicate with it, get module id and capability information, implement receiver bandwidth mode switching, led power control, shutdown and some other functions. this interface requires three signals: a clock line (sclk) that is used for timing, and two unidirectional lines multiplexed with the transmitter (txd, write) and receiver (rxd, read) infrared signal lines. the supported programming sequence formats are listed below: one-byte special commands two-byte write commands two-byte read commands three-byte read commands the one-byte special command sequences are reserved for time-critical actions, while the two-byte write command is predominantly used to set basic transceiver characteristics. more information can be found in the irda document "serial interface for transceiver control, v 1.0a" on irda.org web site. serial interface timing specifications in general, serial interface programming sequences are similar to any clocked-data protocol: there is a range of acceptable clock rates, mea- sured from rising edge to rising edge there is a minimum data setup time before clock ris- ing edges there is a minimum data hold time after clock rising edges recommended programming timing: (4 khz <) fclk < 8 mhz (4 khz is a recommended value, according to the serial interface standard quasi-static programming is possible) tclk > 125 ns (< 250 s, see the remark for quasi- static programming above) tsetup > 10 ns thold > 10 ns the timing diagrams below show the setup and hold time for serial interface programming sequences: protocol specifications the serial interface protocol is a command-based communication standard and allows for the communi- cation between controller and transceiver by way of serial programming sequences on the clock (sclk), transmit (tx), and receive (rx) lines. the sclk line is used as a clocking signal and the transmit/receive lines are used to write/read data information. the pro- tocol requires all transceivers to implement the write commands, but does not require the read-portion of the protocol to be implemented (though all transceiv- ers must at least follow the various commands, even if they perform no internal action as a result). this serial interface follows but does not support all read/ write commands or extended commands, supporting only the special commands and basic write/read com- mands. write commands to the transceiver take place on the sclk and tx lines and may make use of the rx line for answer back purposes. a command may be directed to a single transceiver on the sclk, tx and rx bus by specifying a unique three-bit transceiver address, or a command may be directed to all transceivers on the bus by way of a spe- cial three-bit broadcast address code. the vishay vfir transceiver tfdu8108 will respond to trans- ceiver address 010 and the broadcast address 111 only, and follows but ignores all other transceiver addresses. the transceiver address of vishay fir module TFDU6108 is 001. all commands have a common \"header\" or series of leading bits which take the form shown below. sclk tx 125 ns < tclk s tsetup > 10 ns thold > 10 ns 18496 0 1 1/0 r0 r1 r2 r3 a0 a1 a2 ... sync bits register address or code transceiver address 1=write 0=read first bit sent to transceiver last bit sent to transceiver 18497
vishay TFDU6108 document number 82537 rev. 1.6, 25-jun-04 vishay semiconductors www.vishay.com 21 the bits shown are placed on the tx (data) line and clocked into the transceiver using the rising edge of the sclk signal. only the data bits are shown as it is assumed that a clock is always present, and that the transceiver samples the data on the rising edge of each clock pulse. note: as illustrated in the diagram above, the protocol uses "little endian" ordering of bits, so that the lsb is sent first, and the msb is sent last for register addresses, transceiver addresses, and read/write data bytes. the notation that follows presents all addresses and data in lsb-to-msb order (bits 0, 1, 2, 3, ... 7) unless otherwise stated. one-byte special commands one-byte special commands are used for time-critical transceiver commands, such as full transceiver reset. a total of six special commands are possible, although only one command is available on the tfdu8108 and TFDU6108. two-byte write commands two-byte write commands are used for setting the contents of transceiver registers which control trans- ceiver such as shutdown/enable, receiver mode, led power level, etc. the register space requires four register address bits (r0-3), although three codes are used for controlling transceiver (see above), and the 1111 escape code is for extended commands. the 3-bit transceiver address (a0-3) is for selecting the destination, e.g. 010 to tfdu8108 and 001 to TFDU6108. the second byte is data field (d0-7) for setting the characteristics of the transceiver module, e.g. sir mode (00) or vfir (05) when the register address is 0001. the basic two-byte write command is illustrated below: 0 1 1 r0 r1 r2 r3 a0 a1 a2 sync bits special command code transceiver address write 0 0 stop bits 18498 command module type programming sequence (binary) programming sequence (hex) reset (set all registers to default value) TFDU6108 011 1011 100 00 3b tfdu8108 011 1011 010 00 5b 0 1 1 r0 r1 r2 r3 a0 a1 a2 sync bits register address transceiver address write 0 0 stop bits 1 d0..d7 8-d a t a bits 18499
www.vishay.com 22 document number 82537 rev. 1.6, 25-jun-04 vishay TFDU6108 vishay semiconductors some important serial interface programming sequences are shown below:
vishay TFDU6108 document number 82537 rev. 1.6, 25-jun-04 vishay semiconductors www.vishay.com 23 command TFDU6108 programming sequence (transceiver address: 001) tfdu8108 programming sequence (transceiver address: 010) common ctrl (0000) value (hex) normal (enable all) 0f 011 0000 100 1 11110000 00 011 0000 010 1 11110000 00 shutdown 00 011 0000 100 1 00000000 00 011 0000 010 1 00000000 00 receiver mode (0001) value (hex) sir 00 011 1000 100 1 00000000 00 011 1000 010 1 00000000 00 mir 01 011 1000 100 1 10000000 00 011 1000 010 1 10000000 00 fir 02 011 1000 100 1 01000000 00 011 1000 010 1 01000000 00 apple talk 03 011 1000 100 1 11000000 00 011 1000 010 1 11000000 00 vfir 05 011 1000 100 1 10100000 00 011 1000 010 1 10100000 00 sharp-ir 08 011 1000 100 1 00010000 00 011 1000 010 1 00010000 00 led power (0010) value (hex) 8 ma 1x 011 0100 100 1 00001000 00 011 0100 010 1 00001000 00 15 ma 2x 011 0100 100 1 00000100 00 011 0100 010 1 00000100 00 30 ma 3x 011 0100 100 1 00001100 00 011 0100 010 1 00001100 00 60 ma 5x 011 0100 100 1 00001010 00 011 0100 010 1 00001010 00 125 ma 6x 011 0100 100 1 00000110 00 011 0100 010 1 00000110 00 250 ma 7x 011 0100 100 1 00001110 00 011 0100 010 1 00001110 00 500 ma fx 011 0100 100 1 00001111 00 011 0100 010 1 00001111 00
www.vishay.com 24 document number 82537 rev. 1.6, 25-jun-04 vishay TFDU6108 vishay semiconductors reel dimensions 14017 w 1 w 2 reel hub tape width a max. n w 1 min. w 2 max. w 3 min. w 3 max. mm mm mm mm mm mm mm 24 330 60 24.4 30.4 23.9 27.4
vishay TFDU6108 document number 82537 rev. 1.6, 25-jun-04 vishay semiconductors www.vishay.com 25 tape dimensions in mm 18269
www.vishay.com 26 document number 82537 rev. 1.6, 25-jun-04 vishay TFDU6108 vishay semiconductors 18283
vishay TFDU6108 document number 82537 rev. 1.6, 25-jun-04 vishay semiconductors www.vishay.com 27 ozone depleting substa nces policy statement it is the policy of vishay semiconductor gmbh to 1. meet all present and future national and international statutory requirements. 2. regularly and continuously improve the performance of our products, processes, distribution and operatingsystems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. it is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (odss). the montreal protocol (1987) and its london amendments (1990) intend to severely restrict the use of odss and forbid their use within the next ten years. various national and international initiatives are pressing for an earlier ban on these substances. vishay semiconductor gmbh has been able to use its policy of continuous improvements to eliminate the use of odss listed in the following documents. 1. annex a, b and list of transitional substances of the montreal protocol and the london amendments respectively 2. class i and ii ozone depleting substances in the clean air act amendments of 1990 by the environmental protection agency (epa) in the usa 3. council decision 88/540/eec and 91/690/eec annex a, b and c (transitional substances) respectively. vishay semiconductor gmbh can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. we reserve the right to make changes to improve technical design and may do so without further notice. parameters can vary in different applications. all operating parameters must be validated for each customer application by the customer. should the buyer use vishay semiconductors products for any unintended or unauthorized application, the buyer shall indemnify vishay semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. vishay semiconductor gmbh, p.o.b. 3535, d-74025 heilbronn, germany telephone: 49 (0)7131 67 2831, fax number: 49 (0)7131 67 2423

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